Character storage and display system

ABSTRACT

A system for storing characters of information in a selected form in a storage means which has a plurality of character positions. Characters are recorded in each position in a multibit code and means are provided for storing an additional control bit in each of the character positions. A selected form may be stored in the storage means by storing bits in selected ones of the control bit positions in accordance with a predetermined logical pattern. The state of each control bit is detected and utilized for controlling the field in the storage means in which new characters applied to the system are stored. In particular, the control bits may be utilized to identify tab positions in a particular form or to effect the protection of fixed field characters.

United States Patent Dlxson Teh-Chao Jen Stamford;

Stephen A. Grosky, Monroe; Robert J. Duggan, Monroe, all of, Conn.

Sept. 16, 1968 Aug. 10, 197 1 The Bunker-Rarno Corporation Stamford, Conn.

Continuation-impart of application Ser. No. 727,934, May 9, 1968, now abandoned.

[72] Inventors [21] Appl. No. [22] Filed [45] Patented [73] Assignee [54] CHARACTER STORAGE AND DISPLAY SYSTEM 23 Claims, 8 Drawing Figs.

[52] U.S.Cl 340/1725 [51] Int.Cl G06t'3/l4 [50] FieldofSearch............................................ 340/1725;

Primary Examiner-Raulfe B. Zache Attorney-Frederick M. Arbuckle ABSTRACT: A system for storing characters of information in a selected form in a storage means which has a plurality of character positions. Characters are recorded in each position in a multibit code and means are provided for storing an additional control bit in each of the character positions. A selected form may be stored in the storage means by storing bits in selected ones of the control bit positions in accordance with a predetermined logical pattern. The state of each control bit is detected and utilized for controlling the field in the storage means in which new characters applied to the system are stored. in particular, the control bits may be utilized to identify tab positions in a particular form or to effect the protection of fixed field characters.

l l I l i PATENTED AUG! 0 l8?! SHEET 1 BF 5 QON INVENTOR.

DIXSON TEH-CHAO JEO B STEPHEN A. GROSKY /071 J DUGGAN- ATTORNEY P20 0Z C mooomo ma? lulfl.

PATENTED AUG 10 IQTI SHEET 2 0F 5 CHARACTER STORAGEAND DISPLAY SYSTEM This application is a continuation-in-part of application Ser. No. 727,934 filed May 9, 1968 by Dixon Teh-Chao .Ien, abancloned.

This invention relates to a system for storing characters of information in a desired format, and more particularly to an information storage and display system which provides for the protection of fixed field characters and for a tabbing capability.

This invention is concerned primarily with the type of system wherein an operator at a remote station may key in information to be stored in a data processor or may query the data processor and receive back a replay. A display device is provided, such as for example a CRT or a printer, on which the message which the operator is generating is displayed. When the operator has completed a message and is satisfied that it is accurate, he strikes a transmit key which causes the message, which has been assembled and stored, to be sent to the data processor. The data processor may then generate a reply which is likewise displayed. The Bunker-Ramo Series 200 CRT Input-Output system :is an example of this type of system.

In some applications of such a system the information which is sent to, or received from the processor will be in a particular format. In such an application, it is important that each item of information appear in the proper field since the significance of a particular item of information is recognized by its relative position in a message. It is also desirable that fixed field data which, for example, may identify the items on the form, not be accidentally written over. Stated another way, there is a requirement that a query and response system utilized for this type of application have the ability to protect selected characters and that the system have a tabbing capability.

Systems of this type generally include a visible cursor which indicates to the operator the character position on the display at which the next character will be recorded. It is desirable in such systems to have the capability to rapidly advance the cursor to a desired position by depressing a single key. There are some situations where an entry of fixed length will be made in a particular field of a form. Such entries could, for example, be a one-character check mark of a short, fixed-length answer such as for hair color or eye color. With such forms, operator time can be saved if the system automatically tabs to the beginning of the next variable field entry (i.e. to the next tab point), after the fixed-length variable entry has been completed. Since recording is not to be performed in fixed field areas, it would also be desirable if a capability could be provided to automatically advance the cursor to the next tab point when the cursor enters a fixed-field area. This latter capability could be one way of implementing the automatic tabbing at the end of fixed-length entries.

In the past, systems of this type have utilized a special character to indicate tab points and have used special characters to indicate the beginning and end of protected fields. However, if these special characters are to be preserved for more than one message. the extra character position or positions occupied by these characters will shorten the total number of usable character positions ofstorage and display. In cases where data are to be entered-by their character positions in a line, such as for example where a character is to go into the th or 12th character position, these positions become distorted due to the special character and cannot be readily identified. This method of operation has the further disadvantage that, particularly for the tab character, if it is desired to write data on a line which does not require the tab character, it will be necessary to erase this special character. Under these conditions, the format data will have to be retransmitted with each new message. Other features, such as automatic tabbing are not available in these systems. It is thus apparent that an improved method of providing format information, such as tab positions, in a computer I/O device is required.

It is therefore a primary object of this invention to provide an improved means for providing format information in a computer I/O system.

A more specific object of this invention is to provide tab information in such a system without requiring storage of special characters.

Another object of this invention isto'provide for the protection of fixed field data without requiring storage of special characters.

A further object of this invention is to provide tab points which are not destructive after usage so that each format can be used repeatedly.

Still another object of this invention is to provide an automatic tabbing capability in a system of the type described above.

A still further object of this invention is to provide a means for automatically advancing a cursor bit which appears in a fixed-field entry to the beginning of the next variable field entry.

Another object of this invention is to provide, in a system of the type described above, a capability for rapidly advancing the cursor at a predetermined rate under keyboard control.

In accordance with these objects this invention provides a system for storing characters of information in a selected form which system includes a storage means'which has a plurality of character positions. Characters are recorded in each of these positions in a multibit code and a means is provided for storing an additional'control bit in each of the character positions. A selected form may be stored in the storage means by storing bits in selected ones of the control bit positions in accordance with a predetermined logical pattern. The state of each control bit is detected and utilized for controlling the field in the storage means in which new characters applied to the system are stored. The control bits may also be utilized to protect fixed field characters. For example, if there is a bit in the control bit positionfor a character and there is a bit in the corresponding position of the succeeding character, then circuitry can be provided to inhibit the recording of information in the character position. Similarly, the extra control bit may be utilized to identify a tab point. If there is a control bit for a particular character but the control bit for the succeeding character is zero, logic may be provided to indicate that the first of these characters is a tab point. An extra control bit in each character is thus utilized for format control.

The foregoing and other objects, features and advantages of this invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 is a diagram illustrating how FIGS. lA-1D may be combined to form a composite schematic block diagram of a preferred embodiment of the invention.

FIGS. 1A1D, when combined, form a composite schematic block diagram of a preferred embodiment of the invention.

FIG. 2 is a diagram illustrating a possible display format which may be utilized in conjunction with this invention.

FIG. 3 is a diagram illustrating the format in which characters are stored in the memory of FIG. I for a fixed field followed by a tab point.

FIG. 4 is a diagram illustrating the format in which characte'rs are stored in the memory of FIG. I for a solitary tab point.

Referring now to FIG. ID, it is seen that the system of this invention includes a memory 10 which may, for example, be a rotating magnetic disc or magnetic drum or a recirculating delay line. For the discussion to follow it will be assumed that memory 10 is'a recirculating delay line which is made up of a main portion 10A which is N characters, minus one bit, long; a second section, 103, which is two characters, plus one bit, long; and a third section 10C which is one character long. Delay 10C is in the form of a one character shift register.

Referring now to FIGS. 3 and 4, it is seen that each character stored in memory 10 is made up of seven bits. The

first bit is known as the cursor bit. A bit in this position indicates that this is the next character in memory which is to be read out or written into. The next bit in each character is the mark or control bit. This is the bit of primary interest in this invention and, as will be seen shortly, is utilized for format control. The remaining five bits in each character contain the code for the character itself. 1

From FIGS. 3 and 4 it is also seen that alternate characters in memory 10 are designated AS, for A-slot, and BS, for B- slot. The significance of this is that two or more display devices may be associated with a single memory with characters utilized to control the display on the devices being interlaced in memory 10. In FIGS. 3 and 4 it has been assumed that there are two devices, an A device and a B device, which are associated with the memory. As each character is read from memory 10 it is gated to the appropriate device to control the display thereon. The manner in which this is accomplished will be described shortly.

Referring now to FIG. 2, a display form is illustrated which consists of five lines. The first line contains the fixed field word NAME:." As will be seen shortly a tab point exists in the character position following the colon. The second line has the words AGEz, HT: and WT:. The character following the colon in each of these words is likewise a tab point. The third line of the display has the fixed field words SEX:," HAIR:," and EYES:" with each of these words likewise having a tab point in the character following the colon. The fourth and fifth lines do not contain any fixed field information and may, for example, be used to record additional information on the named individual. However, 'a tab point does appear at an indented position on thefourth line.

In the discussion to follow it will. be assumed that a display such as that shown in FIG. 2, is desired on the face of a cathode-ray tube (CRT) display device. The CRT has a fixed number of character positions on each of its lines and a fixed number of lines, for example 5, in each frame. The recirculation time of delay line 10 is also fixed. Therefore, a clock pulse generating source 11 (FIG. 1D) may be provided, the pulse frequency of which is equal to the rate at which bits pass the write transducer of delay line segment 10A. Signals on output line 12 from pulse source 11 are referred to as bit clock (BC) signals and are applied to increment clock counters 14. There may be a number of interconnected counters which go to make up clock counters 14 such as, for example, a bit counter, a character counter, and a line counter. Several of the outputs from clock counters 14 are of particular interest. Among these is output line 16 which has a signal on when a cursor bit is in a position to be written into. Output line, 18 has a signal on when a mark bit is in a position to be written into while one of the five output lines 20 has a signal on it when one of the bits 131- B respectively of a character is under the write transducer. Clock counters 14 also contain a character toggle which generates an output signal on line 21 when an A-slot character is being written into and an output signal on line 22 when a B- slot character is being written into. The signals on lines 21 and 22 may be utilized to gate output characters from memory to the appropriate display device. At character-l time of each display line a signal appears on line-clock line 23 and at line-1, character-l time of each frame, a signal appears on frameclockline 24. In order to simplify the circuit diagram, no attempt has been made to connect the various clock signals to the points in the circuit at which they are utilized. In stead, lines with suitable letter and numeric designations are shown at each of these points.

. Form Loading Assume initially that it is desired to load the form shown in FIG. 2 into memory 10 and that this form is to bedisplayed ventional manner and utilized to generate a signal on either line'25 or 26 to set device flip-flop 27 (FIG. 1A) to the proper state. For a form to be stored in the B-slots, a signal appears on line 25 setting flip-flop 27 to its ONE state. This results in a signal on B8 output line 28 which is utilized, in a manner to be described shortly, to control the loading of the form into memory 10. The decoding of the address input also causes a LOAD flip-flop (not shown) to be set indicating that the processor is loading information into the system. This flip-flop is reset when an end-of-message code is received from processor 30 resulting in a signalon the ZERO-side output (LOAD') line 31 from the LOAD flip-flop. As will be seen, the LOAD signal is utilized at a number of points in the circuit.

The form information from processor 30 is applied on a bit by bit basis through transmission line 32 to be stored in input butter 34. The position in input buffer 34 at which each bit is stored, is controlled by buffer-load-control circuit 36 through lines 38. The control is such that a bit of new information is always loaded into the rightmost bit position of the buffer which is empty. Line 32 is also connected to butter-control circuit 36 to permit proper stepping of the load control.

When a full character is present in the rightmost position of buffer 34 (Le. when the next bit to be loaded into buffer 34 is to be loaded into a position to the left of the first character position) a signal appears on full character line 40 from control 36. The signal on line 40 is applied as one input to shiftout (50) decode AND gate 42, shift-in (SI) decode AND gate 44, and tab decode AND gate 46. The contents of the rightmost character position of input buffer 34 are applied through lines 48 as another input to each of the AND gates 42-46. The final input to each of these AND gates is cursorbit clock line 16. Therefore, at the first cursor bit time after a full character appears in the rightmost position of buffer 34, AND gates 42-46 are enabled to sample this character to see if it is one of the special characters being looked for.

Assume initially that all flip-flops shown in the circuit, except for flip-flop 27 which was set to its ONE state by a B- device address input, are in their ZERO state. Assume further that an S0 character always precedes an SI character. As will be seen in the discussion to follow an 50 character (which may also be referred to as a second special character) is util ized to indicate the start of fixed field data while an SI character (which may also be referred to as a first special character) is used both to indicate the end of fixed field data and to indicate the character position in which a tab point is to be located. Thus, when a format is to be stored in the system, fixed field data will be stored by applying an character to the system followed by the fixed field data and an SI character. A tab point, not preceded by fixed field data, will be indicated by an S0 character followed immediately by an Sl character.

At the first CB time after an S0 character is stored in the rightmost position of buffer 34, AND gate 42 (FIG. 1A) is fully conditioned to generate an output signal on line 50 which is applied to set flip-flop 52 to its ONE state and is also applied through OR gate 54 and line 56 to buffer control circuit 36 to cause a one character shift-right operation in the buffer. The signal on line 56 is also applied through OR gate 57 and line 59 to reset the SO character in buffer 34. This results in the character following the SO character being moved into the rightmost position of buffer 34. The S0 character thus performs its control function and is then destroyed. Output line 58 from the ONE side of flip-flop 52 is connected through OR gate 60 and line 62 as one input to AND gate 64. A second input to AND gate 64 is MB clock line 18. The final input to AND gate 64 is output line 65 from AND gate 67 (FIG. 1B). The inputs to AND gate 67 are ONE-side output line 66 from load flip-flop 68 and output line 69 from OR gate 71 (FIG. 1A). The inputs to OR gate 71 are output lines 73 and 75 from AND gates 77 and 79 respectively. The inputs to AND gate 77 are BS clock line 22 and output line 28 from the ONE, or B, side of device flipflop 27. The inputs to AND gate 79 are AS clock line 21 and output line 29 from the ZERO, or A, side of flip-flop 27. A signal on line 69 therefore means that the character being written into corresponds to the addressed device. Since it has been assumed that all flip-flops, and therefore load flip-flop 68, are initially in their ZERO state, neither AND gate 64 nor 67 is fully conditioned at this time, and the setting of SO flip-flop 52 causes no action to initially occur.

Load flip-flop 66 is set to its ONE state by a signal on output line 70 from AND gate 72. One input to AND gate 72 is fullcharacter output line 40 from buffer-load-control circuit 36. A second input to AND gate 72 is output line 74 from inverter 76. The input to inverter 76 is buffer-empty output line 78 from load-control circuit 36. A signal therefore appears on line 74 when the buffer is not empty. The final input to AND gate 72 is output line 88 from OR gate 90. The inputs to OR gate 90 are output line 92 fromAND gate 94 (FIG. 1C) and output line 96 from AND gate 98; One input to AND gate 98 is output line 100 from the ZERO side of flipflop 102. As will be seen shortly, flip-flop 102 is in its ZERO state when the system is not looking for a tab bit in response to a tab request from the processor. The other input to AND gate 98 is output line 104 from AND gate 106. The inputs to AND gate 106 are output line 108 from one-character shift register C (FIG. 1D), CB clock line 16 and device-match line 69. Line 108 is, for the recirculating delay line 10, both the memory output and part of the recirculation path to main delay 10A. AND gate 106 is thus fully conditioned to generate an output signal on line 104 when a cursor bit is detected in the character about to be written in memory 10 and the character is for the device presently being written into. It is thus seen that AND gate 98 is fully conditioned to generate an output signal on line 96 when a cursor bit has been detected in memory 10 and the system is not looking for a tab position in response to a request from the processor. It will be seen later that AND gate 94 is fully conditioned to generate a signal on line 92 when, during a time when the system is looking for a tab position in response to a request from the processor, a tab position, or one of certain other selected positions, is located. It is thus seen that AND gate 72 is fully conditioned to set load flip-flop 68 to its ONE state when there is a full character in the rightmost position of input buffer 34, and the position in which it is desired to write the next character has been located. It should at this point be noted that, each time a cursor bit is detected and utilized to cause some operation to be performed, the cursor bit is erased in a manner substantially the same as that for the before-mentioned Bunker-Ramo Series 200. In particular, output line 70 from AND gate 72 is connected as one input to OR gate 109 (FIG. 1C). Output line 111 from OR gate 109 is connected through inverter 113 and line 115 as a conditioning input to gate 117. Therefore, when a signal does not appear on line 70, or on any of the other inputs to OR gate 109, gate 117 is conditioned to apply the memory output on line 108 through line 119 OR gate 122 and line 124 to be stored in memory 10. Line 108, gate 117 and line 119 thus form the recirculation path for the delay line. By blocking this path when a signal appears on line 70, the cursor bit, the detection of which gave rise to this signal, is effectively erased.

At the first mark bit time that there is a signal on line 69 after flip-flop 66 is set to its ONE state, AND gate 64 (FIG. 1A) is fully conditioned to generate an output signal on line I which signal is applied through OR gate 122 and line 124 to cause a mark bit to be recorded in the mark bit position of the character then being written into in memory 10. With an 50 character originally in buffer 34, the setting of load flipflop 68 could only be accomplished as a result of the detection of a cursor bit by AND gate 106 in the character being written into. The mark bit will thus be recorded in the mark bit position for the same character as that in which the cursor bit was detected.

As long as processor 30 continues to apply characters to input buffer 34 at a rate such that a buffer empty signal does not appear on line 78, flip-flop 68 remains in its ONE state causing a conditioning signal to be applied to AND gate 64 during each B-slot time. Thus, once an S0 character is detected, mark bits will continue to be'record'ed in the mark bit position of each subsequent BS character-which is written in memory 10. The characters following the-SO character are applied to memory 10 by utilizing the signal on output line 65 from AND gate 67 as a conditioning input to gate 126. The information input to this gate is output'line 128 from OR, gate 130. The inputs to OR gate 130 are the B lB5 clock lines 20 from clock counters'l4. Output line 132-fr0m gate 126 is connected as a shift input to bufier-load-control circuit 36. Thus, during the B1B5 times of each BS character, when load flipflop 68 is inits ONE state, the bits of the character stored in the rightmost character position of input buffer 34 are shifted out through line 134, OR gate 122 (FlGflA) and line 124 to be recorded in memory 10 (FIG. 1D). This recording occurs until a buffer-empty condition is detected resulting in a signal on line 78 which is applied as one input to AND gate 136 (FIG. 1B). The other inputs to AND gate 136 are cursor-bit clock line 16 and ONE-side output line'66 from load flip-flop 68. Therefore, at the first cursor-bit time after buffer 34 is empty, AND gate 136 is fully conditioned to generate an output signal on line 138 which is applied to reset load flip-flop 68 to its ZERO state. The resetting of flip-flop 68 to its ZERO state terminates the signal on line 66.inhibiting the writing of any further mark bits. It should be noted that, as long as an SI character has not been applied to the system, SO flipflop 52 remains in its ONE state. The signal on line 138 is also applied through OR gate 122 (FIG. 1B) and line:l24 to cause a cursor bitto be recorded in the character position following the last one which was written into.

Nothing further happens until processor 30 applies a new character to input buffer 34. At this time signals again appear onlines 40 and 74. When the cursor bit'which was recorded at the end of the last write operation reaches input line 108 of AND gate 106 (FIG. 1C) all inputs to AND gate 72 are again present resulting in a signal on line 70 which sets load flip-flop 68 to its ONE state. This results in a mark bit being recorded in the mark bit position of the character in which the cursor bit was detected and 'inthe new character being stored in the Bl-BS positions of this character position in memory. Subsequent characters applied to buffer 34 by processor 30 are recorded in memory 10 in a similar manner until a buffer empty condition isagain detected or until an SI character is decoded in the rightmost position of buffer 34.

At the first cursor-bit time after an 81 character is shifted into the rightmost position of buffer 34, AND gate 44 is fully conditioned to generate an output signal on line 140 which signal is applied to reset SO flip-flop 52 'to its ZERO state and to set SI flip-flop 142 to its ONE state. The signal on line 140 is also applied through OR gate 57 and line 59 to reset the SI character in the rightmost position of buffer 34.

Output line 144 from the ONE side of SI flip-flop 142 is connected through OR gate 60 and line 62 as one input to AND gate 65. The resetting of the SI character in buffer 34 does not cause a buffer empty signal to appear on line 78. Therefore, load flip-flop 68 remains in its ONE state. Thus, at the first mark bit time that there is a signal on line 69 following the cursor bit time at which the 8] character is detected, AND gate 64 is fully conditioned to generate an output signal on line 120 which is applied to record a mark bit in the mark bit position of the character then being written into. The signal on output line 65 from AND gate 67 is also applied as one input to AND gate 146, the other input to this AND gate being mark-bit clock line 18. Therefore, at the mark-bit time that a bit is being recorded in memory 10, AND gate 146 is fully conditioned to generate an output signal on line 148 which is applied to reset SI flip-flop 142 to its ZERO state. This removes the signal which was being applied through line 62 to AND gate 64 thus inhibiting the writing of further mark bits into memory 10. At the following 81-85 times the all zeros character, representing the reset Sl character in the rightmost position of input buffer 34, is read into the same character position in memory 10 as that in which the last mark bit was recorded. Subsequently characters read intomemory 10 will not contain mark bits. From the above it is seen that all characters received between an S and SI character will contain a mark bit and will thus be protected as fixed field data. The character position in which the SI character is received will also contain a mark bit. Since the presence of a mark bit in a character followed by a character without a mark bit is recognized, as will be seen later, as a tab point, the character position representing that in which an SI character is received is a tab point. Fixed field information, followed by a tab point, such as is shown in FIG. 3, is in this manner loaded into the system.

The discussion so far has been with reference to the establishing of fixed field data and to the recording of a tab point at the end of this fixed field data. As may be seen from line 4 of FIG. 2, and from FIG. 4, it is also possible to establish a tab point which is not preceded by fixed field data. This is accomplished by applying an S0 character to the system and following it immediately by an SI character. At the first CB time after the SO character is received, a signal appears on line 50 setting flip-flop 52 to its ONE state. The signal on line 50 also causes the SO character in buffer 34 to be reset and a one-character shift right operation to be performed, bringing the SI character into the rightmost position of buffer 34. This shifting occurs during the Bl-B5 times of the character time during which the SO character was detected so that, at the next CB clock time, AND gate 44 is fully conditioned to generate an output signal on line 140. This signal is applied to reset flip-flop 52 to its ZERO state and to set SI flip-flop 142 to its ONE state. The signal on line 140 is also applied through OR gate 57 to reset the SI character in buffer 34.

If load flip-flop 68 is in its ZERO state at this time, nothing further occurs until the character containing the cursor bit is adjacent to the memory write heads. At this time, AND gate 106 will be fully conditioned causing load flip-flop 68 to be set to its ONE state in a manner previously described. At the first MB time following the setting of the load flip-flop that a signal appears on line 69, AND gate 64 is fully conditioned to cause the recording of a mark bit in the character then being written into and AND gate 146 is fully conditioned to cause the SI flip-flop to be reset. The all-zero character, representing the reset SI character, is then read into memory during Bl-B5 time in a manner identical to that previously described.

It should, at this point, be noted that, if the load flip-flop was in its ONE state when the SO character was detected in buffer 34, this means that a character was written into memory during the preceding character time. Thus, the SO character will be detected and erased, and the SI character shifted into the rightmost position of buffer 32 during an A-slot time when a signal does not appear on line 69. The all-zeros character which is shifted out of the memory at this time will thus not be recorded in memory 10. However, the SI character is detected in shift register 34 during the following B-slot time when a signal does appear on line 69. The mark bit and the all-zeros character representing the reset SI character will thus be recorded in memory 10 during this B-slot time in a manner identical to that described above when the load flip-flop was not initially set. If there is another character applied to the buffer following the SI character then this character will be recorded in the next B-slot position. Subsequent characters will be similarly recorded.

From the above it is seen that, when it is desired to record only a tab position, a mark bit is written into the first character position for the selected device which is written into following the receipt of an SI character, thus establishing this position as the tab position. It should be noted that the SO character performs no real function in the above sequence of operations and that atab point not preceded by fixed field data could just as easily be generated by sending only the SI character. However, in the preferred embodiment of the invention, it has been specified that an SI character will always be preceded by an S0 character. Therefore, for the sake of consistency, both characters are generated even through only one is needed.

Tab Operation Uniifirocessor Control The discussion so far has been concerned with the recording of the mark bit in selected positions of memory so as to establish fixed field data and/or tab points of a particular form. Assume now that the mark bits for a desired form have been recorded in memory and that it is desired to record information in this form under processor control. For example, referring to FIG. 2, assume that the form shown therein has been recorded in memory and that it is now desired to write in an individuals name. Assume further that all flip-flops are again in their ZERO state and that a cursor bit has been recorded in the first position of the frame (ie in the position in which the fixed field character N of the word NAME" is stored). As may be seen from FIG. 3 the first tab point is in the character position following the colon of the NAME:" entry.

Processor 20 initially applies a device address to the system which, assuming that the information is to be displayed on the B device, causes device flip-flop 27 to be set to its ONE state. The detection of the device code also causes the LOAD flipflop (not shown) to be set to its ONE state. Since the name applied to the system is to be stored starting at the tab point, the first character applied to the system in this instance is a tab character. The detection of this character in the rightmost position of buffer 34 by AND gate 56 (FIG. 1A) results in an output signal on line 152 which is applied to set flip-flop 102 (FIG. 1C) to its ONE state and is also applied through OR gate 54 and line 56 to reset the tab character in buffer 34 and to move the first character of the name into the rightmost position of the buffer. Flip-flop 102 being in its ONE state decon ditions AND gate 98 thus inhibiting the setting of load flip-flop 68.

Referring to FIG. 1D. it is seen that output line 112 from main memory segment 10A is connected to the ONE-side input of flip-flop and through inverter and line 162 to the ZERO side input of this flip-flop. Flip-flops 155-158 are connected together as a four-bit shift register with CB clock line 16 being connected as a shift input to flip-flop 155 and the B5 line of the clock lines 20 being connected as the shift input to the remaining flip-flops of this register. It should be noted that, since delay 10A is N characters, minus one bit, long, it is actually the mark bit of a character which is on line 112 when a CB clock appears on line 16. Thus, as each mark bit appears on line 112, the state of this bit is set into flip-flop 155, while, during the preceding B5 time, the mark-bit status for the three previously read characters are shifted into flip-flops 156-158 respectively. The change of state in flip-flops 155458 is not, however, completed until the end of respective shift clock times. During CB time, the mark-bit status for the character being read is on line 112. Since there is an additional three character delay between line 112 and the end of delay line 10, the character whose mark bit is stored in flip-flop 158 is in the character which is presently being written into.

It will be remembered that characters associated with a particular device are stored in alternate character positions. Therefore, the bits in flip-flops 155 and 157 are related to one device which will be called the alternate device while the bits in flip-flops 156 and 158 are associated with the device presently being written into. It should also be remembered that the algorithm for fixed field characters is that they have a bit in their mark-bit position and there is a bit in the mark-bit position of the following character, while the algorithm for a tab point is that there is a mark in the mark-bit position of the character but no mark in the mark-bit position of the following character. Therefore, output lines 164 from the ONE side of flip-flop 156 and 166 from the ONE side of flip-flop 158 are connected as the inputs to fixed field AND gate 86. Signals appear on lines 164 and 166 concurrently only when there is a mark bit in both the character presently being written into and in the following character for the same device. A signal on output line 64 from AND gate 86 therefore indicates that the character position presently being written into contains a fixed field character.

Line 166 is also connected as one input to tab-point AND gate 168, the other input to this AND gate being output line 170 from the ZERO side of flip-flop 156. AND gate 168 is thus fully conditioned when the character presently being written contains a mark bit while the following character for the same device does not contain a mark bit, the required condition for recognizing a tab point. Output line 174 from the ONE side of flip-flop 157 and output line 176 from the ZERO side of flip-flop 155 are connected as the inputs to tab-pointin-alternate-slot AND gate 178. AND gate 178 will be fully conditioned during a character time of the character following that presently being written into is a tab point. It should be noted that this character will be for a different device than the device for the character which is presently being written into.

When flip-flop 102 (FIG. 1C) is in its ONE state, as its is after a tab decode occurs in AND gate 46, a signal appears on ONE-side output line 180. This signal is applied as one input to AND gate 94 and through OR gate 182 and line 184 as one input to AND gate 186. The other input to AND gate 186 is cursor-detect output line 104 from AND gate 106. Therefore, the first time that a cursor bit is detected in a character for the device which is being written into after flip-flop 102 is set to its ONE state, AND gate 186 is fully conditioned to generate an output signal on line 188 which signal is applied to set flip-flop 190 to its ONE state. For the example presently being considered, it has been assumed that the cursor bit is in the character position in which the fixed field character N" (see FIG. 3) is stored. Flip-flop 190 will therefore be set to its ONE state when this character is in a position to be written into memory 10. Output line 188 from AND gate 186 is also connected as an input to OR gate 109. Therefore, when a cursor bit is detected during a search-for-tab operation, the cursor bit is erased. As will be seen shortly, when the tab point is located the cursor is rewritten at this point.

Output line 192 from the ONE side of flip-flop 190 is connected as a second input to AND gate 94 and as one input to AND gate 194. A thirdinput to AND gate 94 is CB clock line 16. The final input to AND gate 94 is output line 196 from OR gate 198; Two inputs to OR gate 198 are line clock line 23 and frame clock line 24. The final input to OR gate 198 is tab point output line 200 from AND'gate 168 (FIG. 1D). It is thus seen that AND gate 94 will be fully conditioned when, during a search for a tab point in response to a processor request, and after a cursor bit has been located, either a tab point has been located or the end of a line or frame has been reached. For the example presently being considered, a tab point will be detected in the character following the colon of the fixed field entry "NAME: which at CB time,-results in AND gate 94 being fully conditioned to generate an output signal on line 92 which signal is applied to reset flip-flop 102 to its ZERO state,

through OR gate 199 and line 210 to reset flip-flop 190 to its one input of AND gate 72. If there is a character to be written in buffer 34 at this time, signals will appear on lines 40 and 74 fully conditioning AND gate 72 to generate an output signal ZERO state, and through OR gate 90 (FIG. 1B) and line 88 to v on line 70 which is applied to set load flip-flop 68 to its ONE state. The setting of load flip-flop 68 to its ONE state will result in the character in buffer 34 being stored in memory 10 in the character position at which the tab point was detected and in subsequent characters being stored in succeeding memory positions for the same device until all characters which it is desired to store have been written, at which time a buffer empty condition will occur resulting in a signal on line 138 which is applied to reset the load flip-flop and to cause a cursor bit to be recorded in the first empty character position for the device in memory 10. The manner in which these operations are'performed have been described previously and will not be discussed again at this point. It should be noted that, since both the SO and S] flip-flops are in their ZERO state at this time, AND gate 64 is not fully conditioned during MB time and mark bits are not recorded in the characters which are written. This is as it should be since these character are not fixed field characters.

In the discussion above it was assumed that there was at least one additional character in buffer 34 t0 be recorded when a signal appeared on line 92. If there is no character buffer 34 to be loaded when a signal appears on line 92, AND gate 72 is not conditioned to generate a signal on line 70 and inverter 202 (FIG. 1A) therefore applies a signal through line 204 to one input of AND gate 206. The other input to AND gate 206 is the line 92. AND gate 206 being fully conditioned results in an output signal on line 208 which signal is applied through OR gate 122 and line 124 to cause a bit to be recorded in the cursor bit position of the character then being written into. When a character is subsequently applied to the buffer, the cursor bit written into this tab point position will result in the character being stored in this position in a manner previously described. I

When the processor has completed the writing of the name in the name field, the processor would like to tab to the next position in which data is to be written. However, because of the speed at which the processor may apply data to the system, it is not feasible to provide adequate buffering to permit the system to search indefinitely for a tab point. Therefor, it has been determined that if a tab point is not detected before the end of a line, or the end of a frame, then writing will begin at the beginning of the nextline or frame even though the tab point has not'been located. This is effected by applying signals on lines 23 and 24 as inputs to OR gate 198 (FIG. 1C). However, as may be seen from FIG. 2, the beginning of the second line of a data contains the fixed field entry"AGE. Since fixed field data is not protected against being written into from the processor, the processor cannot apply a single tab character to the system following the writing of the desired name into the system unless it is desired to write over the fixed field at the beginning of the second line. The processor must, instead, apply either two successive tab characters to the system of a special device-control character followed by a tab character. The fixed tab character, or the device control character which effects carriage return and line feed, causes the cursor to advance to the beginning of the second line, while the second tab character causes the cursor to step to the desired position in a manner the same as that described above. The operation under control of the device control character is the same as that for the before-mentioned Bunker-Ramo Series 200 system and will not be described further. The remaining entries in the form shown in FIG. 2 are made under processor control in a similar manner. A tab character is applied to the system at the end of each input entry unless the entry is the last entry on a given line. When the processor recognizes that it has made the last entry for a given line it applies either two successive tab characters to the system or a device controlled character followed by a tab character.

Tab Operation Under The Keyboard Control keyboard output lines 212. The lines 212 which have signals on them in response to the depressing of a given keywill depend on thecode for that key. There is a keyboard 210 associated with each of the devices and the depression of a key on a given keyboard may be recognized causing a signal to be generated which will set device flip-flop 27 (FIG. 1A) to its appropriate state in a conventional fashion. For purposes of the present discussion it will be assumed that flip-flop 27 has been set to its ONE state and that all other flip-flops in the system are initially'in their ZERO state. Assume further that the cursor bit is initially stored in the last character position of the last line of the frame and that it is desired to store a name in memory 10 starting at the tab position following the colon of the fixed field entry NAME:" in the first line.

The form information stored in memory 10 is continuously applied through line 108 to display-selection-control circuit 213. Circuit 213 gates the information under control of A-slot and B-slot clock signals on lines 21 and 22 to appropriate lines 215 leading to display devices 217. The information in the B- slots is thus applied to the B-display device, thus permitting the operator to view the form. A visible cursor also appears on the display screen informing the operator as to the position in the form at which the next character which he enters will be stored and displayed. Under theconditions indicated above, the operator will thus realize that a tab operation is required and will strike a tab key on keyboard 210 resulting in a tab code on line 212 which code, when applied to tab decode AND gate 214 (FIG. 1C), results in a signal on line 216 which is applied through OR gate 182 and line 184 to one input of AND gate 186. When the cursor bit in the last character of the frame is detected, AND gate 106 generates an output signal on line 104 which is applied to fully condition AND gate 186 to generate an output on line 188 which is applied to set flipflop 190 to its ONE state. As indicated previously output line 192 from the ONE side of flip-flop 190 is applied as one input to AND gate 194. CB clock line 16 is a second input to this AND gate and no-fixed-field line 80 is a third input. The final input and gate 194 is output line 218 from OR gate 220. The inputs to OR gate 220 are tab point output line 200 from AND gate 168 (FIG. 1D) and from clock line 24. Therefore, when the N character in the first character position of the frame is reached, OR gate 220 will generate an output signal on line 218 resulting in three of the inputs to AND gate 194 being present. However, since the character N is a fixed field character, there is a signal on lines 84 at this time preventing inverter 82 from generating a signal on line 80. Thus, AND gate 184 is not fully conditioned and the search for a tab point continues. At CB time of the character time when the tab point is detected in the B device character following the colon, AND gate 194 is fully conditioned to generate an output signal on line 222 which signal is applied through OR gate 199 and line 201 to reset flip-flop 190 to its ZERO state and through OR gate 122 and line 124 to record a cursor bit in the tab character position.

Nothing further happens until a new character is keyed in on keyboard 210. The keying-in of this character results in signals appearing on one or more of the lines 212 which signals are applied through OR gate 224 and line 226 to one input of AND gate 228. It is assumed that the character keyedin at this time is not a tab character so that there is no signal on line 216 resulting in inverter 230 generating an output signal on line 232 which is applied to a second input of AND gate 228. It is also assumed that flip-flop 234 is in its ZERO state resulting in a signal on Zero-side output line 236 which is applied as a third input to AND gate 228. Flip-flop 102 (FIG. 1C) being in the ZERO state results in a signal on ZERO-side output line 100 which is applied as a fourth input to AND gate 228 and no-fixed field line 80 is connected as a fifth input to this AND gate. The final input to AND gate 228 is output line 104 from AND gate 106 which has a signal on it when the cursor bit which was previously recorded at the tab point is detected. AND gate 228 is therefore fully conditioned to generate an output signal on line 238 when a key other than the tab key has been depressed on v keyboard 210 and the character position containing the cursor bit has been located in memory 10. The signal on line 238 is applied to set flip-flop 234 to its ONE state. ONE-side output line 240 from flip-flop 234 is connected as one input to AND gate 242 and as the conditioning input to gates 244. The information inputs to gates 244 are B1-B5 clock lines 20. Therefore, when flip-flop 234 is 'in its ONE state, Bl-BS clock signals are applied through gates 244 and lines 246 to control the shifting of the character code on lines 212 through parallel-to-serial converter 248 to line 250. Thus, the first bit of the code on the first of the lines 212 is gated onto line 250 during B1 time, the second bit ofthe code on line 212 onto line 250 at B2 time, and so on. Line 250 is connected through OR gate 122 and line 124 to the write input of memory 10. The character represented by the depressed key on keyboard 210 is thus stored in memory 10.

At CB time of the character following that in which the character was stored, a signal appears on clock line 16, fully conditioning AND gate 242 to generate an output signal on line 252 which signal is applied to the ZERO-side input of flipflop 234'to reset this flip-flop, and through OR gate 122 and line 124 to cause a cursor bit to be recorded in this character position in memory 10. The character represented by the next key depressed on keyboard 210 will be stored in this'character position. Storing of characters in memory 10 proceeds in this fashion until the entire name which it is desired to write in the name field has been recorded at which time the tab key is again depressed. The depressing of the tab key results in flipflop (FIG. 1C) again being set to its ONE state to apply a conditioning input to AND gate 194. The system then starts a search for a tab point which point is located in the character position following the character position in which the colon of the fixed field entry AGE:" is stored. When this occurs AND gate 194 is fully conditioned to generate an output signal on line 122 which causes a cursor bit to be recorded in this character position. A subsequent character keyed into the system is stored in this position.

Assume now that the entering of information has proceeded to the third line and that only one character position is provided for the entering of information on the individuals sex. When this character has been entered, the cursor is advanced to the next character position, the character position in which the letter H of the fixed field entry HAIR" is stored. During the next cycle of the delay line, this cursor bit will be detected resulting in a signal on line 104 which signal is applied as one input to AND gate 259 (FIG. 1B). Since this is a fixed field entry, there is also a signal on line 84 which is applied as the second input to AND gate 259. Also, since an input is not being made from the processor at this time, there is a signal on LOCK line 31 and there is also a signal on cursor-bit clock line 16. The final input to AND gate 259 is output line 261 from inverter 263. A signal appears on this line when the loading of a character form the keyboard has been completed. It is thus seen that under the conditions indicated above, AND gate 259 is fully conditioned to generate an output signal on line 265 which signal is applied to set flip-flop 267 to its ONE state and is also applied through OR gate 109 and line 111 to inhibit the storing of this cursor bit. The cursor bit is thus erased from the character position storing the letter H.

Output line 269 from the one side of flip-flop 267 is connected as one input to AND gate 271. The other inputs to AND gate 271 are CB clock line 16 and no-fixed field line 80. Therefore, when the cursor bit position of the tab character position following the colon of the fixed field entry HAIR:" is reached, AND gate 271 is fully conditioned to generate an output signal on line 273 which signal is applied to reset flipflop 267 to its ZERO state and through OR gate 122 (FIG. 1A) and line 124 to cause a cursor bit to be recorded in memory 10. The circuit is thus seen to have an automatic tabbing capability which comes into operation when the cursor is advanced into a fixed field entry. Whenever the cursor enters a fixed field entry, it will automatically be advanced to the next succeeding tab point. This is a useful capability in that it'eliminates the need for the operator to perform a tab operation at the end of fixed length entries.

Another use of this automatic tabbing capability will now be described. Assume that after the operator has finished entering information on the first three lines of the form shown in FIG. 2, he determines that he has no additional information to enter and wishes to rapidly advance the cursor to the first tab point of the frame so as to begin making an entry for a new individual. This may be accomplished by depressing a SCAN key on keyboard 210. The depressing of this key results in a scan code on line 212 which fully conditions scan-decode AND gate 279 to generate an output signal on line 281 which signal is applied as one input to AND gate 283. The other inputs to this AND gate are cursor detected line 104 and LOCK line 31. Therefore, when a cursor bit is detected while the scan key is depressed, AND gate 283 generates an output signal on line 285 which signal is applied through OR gate 109 and line 111 to effect the erasure of the detected cursor bit. Output line 289 from the ONE side of flip-flop 287 is connected as one input to AND gate 291. At the next cursor bit time this AND gate is fully conditioned to generate an output signal on line 293 which is applied to reset flip-flop 287 to its ZERO state and through OR gate 122 (FIG. 1A) and line 124 to cause a cursor bit to be recorded in the next character position. If the SCAN key remains depressed, during the next revolution of the delay line memory this cursor bit will likewise be detected and erased and the cursor bit recorded to the next character position. It is thus seen that the cursor bit will be stepped rapidly through the memory as long as the SCAN key is depressed.

The operator may monitor the advance of the cursor bit on the screen of the display and release the SCAN key when the cursor reaches a desired position. However, since the rate at which the cursor is moving, which depending on the recirculation rate of the delay line, could approach 100 characters-persecond, human reflexes are not fast enough to permit the SCAN key to be released at precisely the required instant for the cursor to end up in the desired position. The recommended procedure is thus to release the SCAN key while the cursor is in the last fixed field entry before the desired tab point. For example, for the cursor to end up in the first tab point of a frame, the SCAN key would be released while the cursor is in the fixed field entry NAME. The automatic tab circuit described above would then take over to advance the cursor to the desired tab point.

While in the description above, the cursor was advanced one character position for each revolution of the delay line while the SCAN key was depressed, the cursor may be moved at lower speed by inhibiting the output from AND gate 283 for a predetermined number of revolutions of the delay line between each output. This would require and additional flipflop which is set by the output from AND gate 283 and is reset by a delayed form of this signal. The ZERO-side output of this flip-flop would be one of the conditioning inputs to AND gate From the above it can be seen that there are at least three significant differences when data is being applied to the system from the keyboard rather than from the processor. First, since inputs from the keyboard occur at a relatively low rate, a buffering problem does not arise and the system can therefore search an entire frame for a tab point rather than being limited to a single line. Thus, only the frame clock 24 is applied as an additional input to OR gate 220 (FIG. 1C) rather than both the frame clock and the line clock as was the case for processor input. Second, fixed field data is protected against being written into from keyboard 210. Therefore, nofixed-field line 80 is applied as one input to AND gate 194, inhibiting the storage of a cursor bit in a position if that position contains fixed field data. No-fixed-field line 80 is also applied as one of the inputs to AND gate 228 (FIG. 18) Therefore, flip-flop 234 cannot be set to its ONE state to pass a character from the keyboard into memory is a fixed field character is adjacent to the memory write heads. Third, since form information is not being entered into memory from the keyboard, a situation will not arise when the cursor need be in a fixed field entry. Therefore, when the system is operating under keyboard control, an automatic tabbing capability is provided which causes the cursor to be advanced to the next succeeding tab point whenever the cursor appears in a fixed field entry.

Message Transmit Operation When the operator at a device has completed the keying-in of a message in, for example, the form shown in FIG. 2, and has verified the message by viewing it on the display, he may wish to transmit this message to processor 30. This is accomplished by depressing a transmit key on keyboard 210. The striking of this key causes all cursor marks in memory 10 for the device associated with the keyboard to be cleared and causes a cursor mark to be recorded at the beginning of the message. Where the system isoperating in a polling mode from the processor, and the processor is ready to receive the message, transmit flip-flop 260 (FIG.--1C) is set to its ONE state. If the system is not operatingain: a polling mode, then, when the rewriting of the cursor mark has been completed, a signal is applied to set the transmit flip-flop to its ONE state. The above described sequence of operation is substantially the same as that which occurs when a transmit operation is to be performed in the before-mentioned:Bunker-RamO Series 200 system, and will, therefore, not be-described further at this point. The particular manner in which these operations are performed does not form part of the present invention.

It should be noted that device flip-flop 27 was set to the appropriate state when the keying-in operation began. Transmit flip-flop 260 being in its ONE state results in a signal on ON E- side output line 262 which signal is applied as one input to AND gate 264 and through OR gate 182 and line 184 to ONE input of AND gate 186. When the cursor bit which was recorded at the beginning of the first character of the message for the selected device is detected on memory output line 108, AND gate 106 is fully conditioned to generate an output signal on line 104 which is applied to the other input of AND gate 186. AND gate 186 being fully conditioned generates an output signal on line 188 which is applied to set flip-flop 190 to its ONE state. The resulting output signal on line 192 is applied as a second input to AND gate 264, as one input to AND gate 266 (FIG. 1D), and through inverter 268 and line 270 as one input to AND gate 272.

In order to conserve transmission time to processor 30, the system, as will be seen shortly, has been designed to suppress the transmission of noninformation carrying characters. The processor is thus able to identify the significance of particular information by its position'in the message only by detecting tab points and recognizing that, when a tab point is received, information following the tab point is-for the next succeeding field. However, since a tab point is stored in the same character position as an information -character,-it would normally be necessary to transmit two characters during the same character time in order to convey all information. In order to overcome this particular problem, the system makes use of the fact that characters associated with a particular device are stored in alternate character positions-and that, at any given time, transmission will only be with respect to one of the devices. The system therefore recognizes the presence of a tab point one character position ahead of the time at which the character is to be sent to the output buffer and sends the tab character code to the buffer during this advanced character time. The circuitry for accomplishing the above described sequence of operations will now be described.

Assume first that the character position in which the cursor has been stored, the first character position of the message is also a tab point. One character time before the cursor of this character appears on output line 108 from one-character shift register 10C (FIG. 1D) the cursor bit appears on output line 116 from delay 10B. Line 116 is connected as one input to AND gate 274, the other inputs to this AND gate being CB clock line 16 and output line 275 from inverter 277. The input to inverter 277 is line 67. Therefore, AND gate 274 is conditioned at the alternate slot, in this case A-slot, time. Since there is a one character delay in register 10C, a B-slot character appears on line 116 at this time, output line 276 from AND gate 274 is connected as a second input to AND gate 272. It should be noted that flip-flop 190 has not yet been set to its ONE state and there will, therefore, be a signal on output line 270 from inverter 268 at this time. Since there is a tab point in the alternate slot at this time, AND gate 178 is generating an output signal on line 278 which is applied to fully condition AND gate 272 to generate an output signal on line 280. The signal on line 280 is applied through OR gate 282 and line 284 to tab-code generator'286 (FIG. 1C). The tab code generated by generator 286 is applied through line 288, OR gate 290 and line 292 to be stored in output buffer 294 (FIG. 18). Characters in output buffer 294 are transmitted to the processor in a manner substantially identical to the manner in which characters are transmitted in the beforementioned Bunker-Ramo Series 200 system. A tab code in the first character of the message is in this manner applied to the output buffer one character time before the character itself is sent to the buffer.

When the character containing the cursor appears on line 108, flip-flop 190 is set to its ONE state in a manner previously described. As indicated previously, two of the inputs to AND gate 264 (FIG. 1C) are output line 192 from the ONE side of flip-flop 190 and output line 262 from the ONE side of transmit flip-flop 260. A third input to AND gate 264 is output line 296 from the ONE side of flip-flop 298 (FIG. ID). Flip-flop 298 is set to its ONE state by a signal on output line 300 from AND gate 302. The inputs to AND gate 302 are output line 304 from OR gate 308 and CB clock line 16. The inputs to OR gate 308 are output lines 310 from the 81-35 bit positions in one-character shift register 10C. Thus, AND gate 302 is fully conditioned to set flip-flop 298 to its ONE state only if the character stored in register 10C, the character which is about to appear on line 108, is not a blank character. At any CB time when a signal does not appear on line 300, flip-flop 298 is reset to its ZERO state. Line 296 being an input to AND gate 264 inhibits the transmission of blank characters to the processor.

A fourth input to AND gate 264 is line 69. It will be remembered that a signal on line 69 means that the character presently appearing on line 108 is for the proper device. The final input to AND gate 264 is output line 128 from OR gate 130 (FIG. 1B). B1B5 clock lines 20 are the inputs to OR gate 130. Therefore, AND gate 264 generates an output signal on line 312 during BlB5 times when both flip-flops 194 and 260 are in their ONE state, when the character in register 10C is a nonblank character, and when the character in register 10C is for the proper device. The signal on line 312 is applied as the conditioning input to gate 314. The information input to gate 314 is memory output line 108. Therefore, when a signal appears on line 312, gate 314 is conditioned to apply the output from the memory through line 316, OR gate 290 and line 292 to be stored in output buffer 294 (FIG. 1B). The characters of the message stored in memory 10 are in this manner transmitted to output buffer 294.

Each time a tab point is detected in the alternate character slot (the character which is about to be read into one character shift register 10C), a signal is applied through line 278 to ONE input of AND gate 266 (FIG. 1D). Once cursor flip-flop 190 has been set to its ONE state, a signal is applied through line 192 to a second input of AND gate 266. The final inputs to this AND gate are-output line 262 from the ONE side of transmit flip-flop 260 and line 275. It will be remembered that a signal appears on line 275 when an alternate slot character is in position to be written into. When AND gate 266 is fully conditioned, it generates an output signal on line 318 which is applied through OR gate 282 and line 284 to energize tab code generator 286 (FIG. 1C). This results in the tab code being applied through line 288 OR gate 290 and line 292 to be stored in output buffer 294. The tab code is thus stored one character time ahead of the character in which it is contained.

The above described sequence of operations continues until the end of a frame is reached at which time a frame clock appears on line 24. This clock is applied as one input to AND gate 320 (FIG. 1C). The other inputs to AND gate 320 are output line 192 from the ONE side of flip-flop 190 and output line 262 from the ONE side of flip-flop 260. Output line 322 from AND gate 320 is applied to reset transmit flip-flop 260 to its ZERO state and through OR gate 199 and line 201 to reset flip-flop 190 to its ZERO state. The system is thus restored to its initial condition.

In the discussion so far it has been assumed that memory 10 is being utilized to service two different display devices. The system may, however, be utilized with only a single display device. In order to operate in this way, while still making full utilization of all memory positions in memory 10, an odd number of memory positions is provided so that, for l revolution of the memory, the A-slot positions will be read while, for the next revolution of the memory, the B-slot positions will be read. It is of course possible to operate with more than two devices. Under these circumstances two or more character positions would be interspersed between the succeeding character positions for a given device.

In the discussion so far it has also been assumed that the processor alone can write form information into memory 10 and that the processor will remember the form so that it will not attempt to write over fixed field information unless there is an express intent to do so. Therefore, fixed field information is protected only against being written over from keyboard 210. Under certain conditions it may be desirable to provide the ability to enter form information into memory from keyboard 210 or to protect fixed field information against being written into from the processor except when an indication is received that form information is being recorded. The circuitry of the system may be altered in accordance with the concepts of the invention to permit either of these modifications.

The control bits in the illustrative embodiment of the invention presented above has been utilized to identify fixed field information and tab points. It is apparent that these control bits could also be utilized to indicate other types of form information such as capital letters, carriage return, line feed, or the like by recognizing other logical patterns in the control bit position or by assigning other significance to the indicated control bit patterns. One or more additional control bits may also be provided for each character if additional control functions are required.

It should also be apparent that, while in the embodiment of the invention described above only a scan right capability has been disclosed, the principle of this invention may be expanded to provide either a scan left or a scan right capability as well as step left and step right.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What we claim is:

1. A system for storing characters of information in a selected form having a plurality of fields comprising:

storage means having a plurality of character positions each adapted to store a multibit coded character;

an additional control bit position provided as part of each of said character positions; and

means for storing a selected form in said storage means, said means including means for storing bits in said control bit positions for selected ones of said characters in accordance with a predetermined logical pattern.

2. A system of the type described in claim I wherein the beginning of each field in a selected form is identified as a tab point, and wherein said means for storing bits includes means for storing a bit in the control bit position for the character at the tab point and for assuring that the control bit position of the following character is blank.

3. A system of the type described in claim I wherein characters in a selected field of the form may be designated as protected fixed field characters, and wherein said means for storing bits includes means for storing a bit in the control bit position of each fixed field character and for assuring the presence of a bit in the control bit position of the character succeeding each fixed field character.

4. A system of thetype described in claim 1 including means for detecting the state of each of'said control bits;

means for applying new characters to said system; and

means responsive to the detected control bits for controlling the fields in said storage means in which said new characters are stored.

5. A system of the type described in claim 4 wherein said field controlling means is operative in response to a predetermined control bit configuration for inhibiting the storing of a new character in a particular character position.

6. A system of the type described in claim 5 including means for storing said new characters in said storage means;

means for indicating the character position in said storage means in which the next new character applied to the system is to be stored; and

means responsive to the presence of said indicating means in a character position having said predetermined control bit configuration for automatically advancing the indicating means to the next succeeding character position.

7. A system of the type described in claim 6 wherein said automatic advancing means is operative to continue advancing said indicating means until said indicating means reaches a character position which does not contain said predetermined control bit configuration.

8. A system of the type described in claim 7 wherein said indicating means is a cursor bit stored in the character position in which the next new character is to be stored; and

wherein said automatic advancing means includes means for erasing the cursor in the character position having said predetermined control bit configuration and for rewriting the cursor in the corresponding bit position of the following character.

9. A system of the type described in claim 7 including scan indicating means; and

means responsive to said scan indicating means for advancing said character position indicating means at a predetermined rate.

10. A system of the type described in claim 9 wherein said character position indicating means is a cursor bit stored in the next character position to be written into; and

wherein said advancing the means which is responsive to said scan indicating means includes means operative at selected times when the cursor is detected for erasing the cursor and for rewriting it in the followingcharacter position, the rate at which the cursor is advanced being dependent on the interval selected between operations of said erasing and rewriting means.

11. A system of the type described in claim 10 wherein said advancing means includes means responsive to the removal of said scan indicating means for terminating the advancing of said cursor; and

wherein said automatic advancing means is operative to further advance the cursor in response to the terminating of the scan in a character position having said predetermined control bit configuration.

12. A system of the type described in claim 5 wherein characters may be applied to said system from a plurality of different sources, and wherein the inhibiting of writing in a character position having said predetermined control bit configuration is effective only for characters derived from a selected one or more of said sources.

13. A system of the type described in claim 4 wherein said field controlling means includes means for recognizing a predetermined control bit configuration to identify a particular character position as a tab position.

14. A system of the type described in claim 13 wherein said means for applying new characters to said system includes means for applying a tab character to the system; and

including means for detecting said tab character;

means responsive to the detection of said tab character for searching said storage means for the next tab position following the last character position which was written into; and

means responsive to the detection of the next tab position for causing characters applied to the system following the tab character to be stored starting at the detected tab position.

out the form information stored in said storage means W: the other Information stored therein, said reading out means including means for detecting the control bit of a character position prior to the time that the remaining bits of the character position are detected, means responsive to said detecting means for determining if the control bit pat tern for the character position and those adjacent to it represents selected form information, and means responsive to the determining that the control bit pattern does represent selected form information for transmitting said form information ahead of the character'in the remainder of the character position.

16. A systemof the type described in claim 15 wherein the succeeding characters of a given message are stored in character positions of said memory means which positions are separated from each other by at least one alternate character position, and including means for enabling said detecting and determining means only during alternate character times so as not to interfere with the transmission of said other information.

17. A system of the type described in claim 1 wherein said form storing means includes means for applying a first special character to said system, means for detecting the application of said first special character to the system, and means responsive to the detection of said first special character for storing a bit in the control bit position of the next character in said storage means to be written into.

18. A system of the type described in claim 17 wherein said form storing means includes means for applying a second special character to said system, means for detecting said second special character, and means responsive to the detection of said second special character for causing bits'to be recorded in the control bit position of each subsequent character written into said storage means.

19. A system of the type described in claim 18 wherein said first special character is always received after said second special character; and

wherein said form storing means includes means responsive to the detection of said first special character for terminating the storing of bits'in the controlbitposition of characters whereby bits 'are recorded in the control bit position of each character written into the storage means between the receipt of a second special character and the receipt *of a first special character and in the first character position written into after the receipt of the first special character, but bits are not recorded in the control bit position of subsequently written characters.

20. A system of the type described in claim 19 whereinthe characters written between the receipt of said second special character and the receipt of said first special character are fixed field characters.

21. A system of the type described in claim 17 wherein the character position in which a control bit is recorded after the receipt of said first special character is a tab point for said selected form.

22. A system of the type described in claim 1 including a display device; and

means for applying the information stored in said storage means to control the display on said display device. 23. A system of the type wherein information is stored in a storage means in at least one selected form'which form has both fixed and variable fields, said system including means for indicating the character position in which the next character applied to the system is to be stored, characterized by:

means for detecting that the indicating means has been advanced beyond the end of a given variable field; and

means responsive to said detecting means for automatically advancing said indicating means to the beginning of the next variable field. 

1. A system for storing characters of information in a selected form having a plurality of fields comprising; storage means having a plurality of character positions each adapted to store a multibit coded character; an additional control bit position provided as part of each of said character positions; and means for storing a selected form in said storage means, said means including means for storing bits in said control bit positions for selected ones of said characters in accordance with a predetermined logical pattern.
 2. A system of the type described in claim 1 wherein the beginning of each field in a selected form is identified as a tab point, and wherein said means for storing bits includes means for storing a bit in the control bit position for the character at the tab point and for assuring that the control bit position of the following character is blank.
 3. A system of the type described in claim 1 wherein characters in a selected field of the form may be designated as protected fixed field characters, and wherein said means for storing bits includes means for storing a bit in the control bit position of each fixed field character and for assuring the presence of a bit in the control bit position of the character succeeding each fixed field character.
 4. A system of the type described in claim 1 including means for detecting the state of each of said control bits; means for applying new characters to said system; and means responsive to the detected control bits for controlling the fields in said storage means in which said new characters are stored.
 5. A system of the type described in claim 4 wherein said field controlling means is operative in response to a predetermined control bit configuration for inhibiting the storing of a new characteR in a particular character position.
 6. A system of the type described in claim 5 including means for storing said new characters in said storage means; means for indicating the character position in said storage means in which the next new character applied to the system is to be stored; and means responsive to the presence of said indicating means in a character position having said predetermined control bit configuration for automatically advancing the indicating means to the next succeeding character position.
 7. A system of the type described in claim 6 wherein said automatic advancing means is operative to continue advancing said indicating means until said indicating means reaches a character position which does not contain said predetermined control bit configuration.
 8. A system of the type described in claim 7 wherein said indicating means is a cursor bit stored in the character position in which the next new character is to be stored; and wherein said automatic advancing means includes means for erasing the cursor in the character position having said predetermined control bit configuration and for rewriting the cursor in the corresponding bit position of the following character.
 9. A system of the type described in claim 7 including scan indicating means; and means responsive to said scan indicating means for advancing said character position indicating means at a predetermined rate.
 10. A system of the type described in claim 9 wherein said character position indicating means is a cursor bit stored in the next character position to be written into; and wherein said advancing the means which is responsive to said scan indicating means includes means operative at selected times when the cursor is detected for erasing the cursor and for rewriting it in the following character position, the rate at which the cursor is advanced being dependent on the interval selected between operations of said erasing and rewriting means.
 11. A system of the type described in claim 10 wherein said advancing means includes means responsive to the removal of said scan indicating means for terminating the advancing of said cursor; and wherein said automatic advancing means is operative to further advance the cursor in response to the terminating of the scan in a character position having said predetermined control bit configuration.
 12. A system of the type described in claim 5 wherein characters may be applied to said system from a plurality of different sources, and wherein the inhibiting of writing in a character position having said predetermined control bit configuration is effective only for characters derived from a selected one or more of said sources.
 13. A system of the type described in claim 4 wherein said field controlling means includes means for recognizing a predetermined control bit configuration to identify a particular character position as a tab position.
 14. A system of the type described in claim 13 wherein said means for applying new characters to said system includes means for applying a tab character to the system; and including means for detecting said tab character; means responsive to the detection of said tab character for searching said storage means for the next tab position following the last character position which was written into; and means responsive to the detection of the next tab position for causing characters applied to the system following the tab character to be stored starting at the detected tab position.
 15. A system of the type described in claim 1 including means for reading out the form information stored in said storage means with the other information stored therein, said reading out means including means for detecting the control bit of a character position prior to the time that the remaining bits of the character position are detected, means responsive to said detecting means for determining if the control bit pattern for the character position and those adJacent to it represents selected form information, and means responsive to the determining that the control bit pattern does represent selected form information for transmitting said form information ahead of the character in the remainder of the character position.
 16. A system of the type described in claim 15 wherein the succeeding characters of a given message are stored in character positions of said memory means which positions are separated from each other by at least one alternate character position, and including means for enabling said detecting and determining means only during alternate character times so as not to interfere with the transmission of said other information.
 17. A system of the type described in claim 1 wherein said form storing means includes means for applying a first special character to said system, means for detecting the application of said first special character to the system, and means responsive to the detection of said first special character for storing a bit in the control bit position of the next character in said storage means to be written into.
 18. A system of the type described in claim 17 wherein said form storing means includes means for applying a second special character to said system, means for detecting said second special character, and means responsive to the detection of said second special character for causing bits to be recorded in the control bit position of each subsequent character written into said storage means.
 19. A system of the type described in claim 18 wherein said first special character is always received after said second special character; and wherein said form storing means includes means responsive to the detection of said first special character for terminating the storing of bits in the control bit position of characters whereby bits are recorded in the control bit position of each character written into the storage means between the receipt of a second special character and the receipt of a first special character and in the first character position written into after the receipt of the first special character, but bits are not recorded in the control bit position of subsequently written characters.
 20. A system of the type described in claim 19 wherein the characters written between the receipt of said second special character and the receipt of said first special character are fixed field characters.
 21. A system of the type described in claim 17 wherein the character position in which a control bit is recorded after the receipt of said first special character is a tab point for said selected form.
 22. A system of the type described in claim 1 including a display device; and means for applying the information stored in said storage means to control the display on said display device.
 23. A system of the type wherein information is stored in a storage means in at least one selected form which form has both fixed and variable fields, said system including means for indicating the character position in which the next character applied to the system is to be stored, characterized by: means for detecting that the indicating means has been advanced beyond the end of a given variable field; and means responsive to said detecting means for automatically advancing said indicating means to the beginning of the next variable field. 